Electronic calculator or digital processor chip with combined functions for constant, keyboard and control bit

ABSTRACT

An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes an data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. A special circuit is used which combines several data and control functions including transfer of constants used in calculations from the ROM to the data registers, transfer of keyboard or other data from parallel input lines to an accumulator register or data memory, or to the adder for test or compare, and selection of one of four bits of a digit in data memory for set or reset. 
     
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SUBJECT                     COLUMN No.                                    
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RELATED CASES                                                             
BACKGROUND OF THE INVENTION                                               
SUMMARY OF THE INVENTION                                                  
BRIEF DESCRIPTION OF THE DRAWINGS                                         
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT                               
The Overall System                                                        
The System Block Diagram                                                  
System Timing                                                             
The Data Memory                                                           
The Adder                                                                 
The Adder Input Select                                                    
The Accumulator and RAMY Y Registers                                      
The Data Path Control PLA                                                 
The Status Logic and Status Latch                                         
Generating the ROM Address                                                
The Program Counter                                                       
The Subroutine Register                                                   
The ROM Page Address Register and Buffer                                  
The Address Controls                                                      
The Keyboard Input                                                        
The Control-Keyboard-Bit Logic                                            
The RAM Page Address                                                      
The ROM and ROM Page Address Decoder                                      
The ROM/RAM Word Decoder                                                  
The D Output Register                                                     
The Accumulator Output Register and                                       
Segment Decoder                                                           
The Power-Up-Clear Circuit                                                
The Program Counter Feedback                                              
The Clock Generator                                                       
Details of Logic Blocks                                                   
The Instruction Set                                                       
Instruction Word Execution Timing                                         
The MOS/LSI Chip                                                          
The Chip Test Functions                                                   
TABLE OF INSTRUCTIONS                                                     
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RELATED CASES

This application discloses subject matter related to that disclosed andclaimed in the following U.S. Patent applications, all filed herewithand assigned to Texas Instruments Incorporated, the assignee of thisinvention: Ser. Nos. 525,236, 525,249, 525,250, 525,244, 525,238,525,247, and 525,246.

BACKGROUND OF THE INVENTION

The invention relates to calculator or digital data processing systems,and particularly to an improved MOS/LSI semiconductor chip for use insuch systems.

Electronic calculator systems of the type having all of the mainelectronic functions within a single large scale integrated (LSI)semiconductor chip, or a small number of chips, are described in thefollowing prior applications or patents assigned to Texas InstrumentsIncorporated: U.S. Pat. No. 3,819,921, by Kilby et al., for "MiniatureElectronic Calculator," based on an application originally filed Sept.29, 1967; Ser. No. 163,565, filed July 19, 1971 by Boone and Cochran,for "Variable Function Programmed Calculator" (now Ser. No. 420,999,filed Dec. 3, 1973); Ser. No. 400,473, filed Sept. 24, 1973, by Bryantfor "Digit Mask Logic In Electronic Calculator Chip" now U.S. Pat. No.3,892,957 issued July 1, 1975; Ser. No. 400,437, filed Sept. 24, 1973,by Vandierendonck, Fisher and Hartsell for "Electronic Calculator WithDisplay And Keyboard Scanning;" Ser. No. 397,060, filed Sept. 13, 1973by Cochran and Grant, for "Multi-Chip Calculator System" now U.S. Pat.No. 3,900,722 issued Aug. 19, 1975; and others.

These prior inventions have made possible vast reductions in cost andsize, and increases in functions, in electronic calculators. Manymillions of such calculators have been produced. The efforts to reducemanufacturing costs and increase the functions available to the user arecontinuing. Particularly, it is desirable to provide a basic chipstructure that is quite versatile and can be used for many differenttypes of calculators and similar digital processing equipment. Thispermits a single manufacturing facility to produce large quantities ofthe same devices, differing only in a single mask change, to producedozens of different variations, while still maintaining large volumecost advantages.

The previous MOS/LSI calculator chips as referred to above weregenerally register organized in that a single instruction word operatedon all of the digits in a given register. A more versatile approach isto make the machine "digit organized," operating on one digit at a time.For example, it may be desired to test or set a particular one bit flag.In a register machine an entire thirteen digit register must beaddressed and masked to implement this, whereas a digit organizedmachine may access only the needed digit or bit. An example of acalculator chip of such nature is referred to at pages 31-32 of"Electronics," Sept. 25, 1972, by Rockwell.

SUMMARY OF THE INVENTION

An MOS/LSI semiconductor chip for providing the functions of anelectronic calculator or digital processor includes a data storage RAM,a ROM for program instruction storage, an arithmetic unit for performingoperations on data, and control circuitry for defining the functions ofthe machine in response to instructions from the ROM as well asconditions in the machine and inputs from external. Input and outputterminals are provided, as for keyboard input and display output. Theoperation is digit oriented in that an instruction accesses one digit ofthe RAM. A special circuit is used which combines several data andcontrol functions including transfer of constants used in calculationsfrom the ROM to the data registers, transfer of keyboard or other datafrom parallel input lines to an accumulator register or to the adder fortest or compare, and selection of one of four bits of a digit in datamemory for set or reset.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asother features and advantages thereof, will be best understood byreference to the detailed description which follows, read in conjunctionwith the accompanying drawings, wherein:

FIG. 1 is a pictorial view of a small hand-held calculator in which thesystem of the invention may be utilized;

FIG. 2 is a block diagram of the system of the calculator of FIG. 1;

FIG. 3 is a detailed block diagram of an electronic system using theinvention, in particular the digital processor chip 15 of FIG. 2;

FIG. 4 is a timing diagram in the form of a graph of voltage vs. timefor clock voltages used in the system of FIG. 3;

FIG. 5 is a detailed electrical diagram of the RAM 25, RAM page decoder29 and RAM write control 70 of FIG. 3;

FIG. 6 is a detailed logic diagram of the adder 50, adder input select51, accumulator 52 and RAM Y register 40 of FIG. 3;

FIG. 7 is a detailed logic diagram of the control PLA 60 of FIG. 3;

FIG. 8 is a detailed logic diagram of the status logic 66 of FIG. 3;

FIG. 8a is a detailed electrical diagram of a complex gate 66-1 of FIG.8;

FIG. 9 is a detailed logic diagram of the program counter 36 andsubroutine register 43 of the system of FIG. 3;

FIG. 10 is a detailed logic diagram of the page address register 46 andthe address buffer 47 of FIG. 3;

FIG. 11 is a detailed logic diagram of the address controls 48 andkeyboard input 75 of the system of FIG. 3;

FIG. 12 is a detailed logic diagram of the CKB logic 56 of FIG. 3;

FIG. 12a is a detailed electrical diagram of one of the complex gates56-8 of FIG. 12;

FIG. 13 is a detailed logic diagram of the RAM page address register 73of FIG. 3;

FIG. 14 is a detailed electrical diagram of the ROM 24 and the ROM pagedecoder of FIG. 3;

FIG. 15 is a detailed electrical diagram of the ROM/RAM word addressdecoder 27 and the data select 39 of FIG. 3;

FIG. 16 is a detailed electrical diagram of the output register 84 andoutput buffers 86 of FIG. 3;

FIG. 17 is a detailed electrical diagram of the output register 62 andthe output buffers 65 of FIG. 3;

FIG. 18 is a detailed logic diagram of the power up clear circuit 82 ofFIG. 3;

FIG. 19 is a detailed logic diagram of the feedback circuit for theprogram counter 36 of FIG. 3;

FIG. 20 is a block diagram of the clock generator 80 of FIG. 3;

FIGS. 21a to 21j are detailed electrical diagrams of logic circuits usedin FIGS. 5-20;

FIG. 22 is a representation of the instruction word used in the systemof the invention;

FIG. 23 is a Karnaugh map of instruction words typically used in thesystem of the invention;

FIG. 24 is a timing diagram showing several instruction cycles in theoperation of the system of FIGS. 1-21;

FIG. 25 is a schematic representation of part of the circuitry of theinvention, arranged to show timing of various events in the system ofFIGS. 1-21; and

FIG. 26 is a top view, greatly enlarged, of an MOS/LSI semiconductorchip incorporating all of the circuitry of the system of FIGS. 3 and5-21.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENT The Overall System

Referring to FIG. 1, a small electronic calculator in which the digitalprocessor of the invention can be used is shown, comprising a housing 10of molded plastic or the like, with a keyboard 11 and a display 12. Thekeyboard includes number keys 0-9, a decimal point key, and severalstandard operation keys such as +, -, =, ×, ÷, C (clear), etc. In apreferred embodiment, the calculator system is designed to performscientific functions, so keys such as EE (enter exponent), √x, X², ^(x)√y, Y^(x), SIN, COS, TAN, LOG, etc., may be included in the keyboard 11.Many other functions may be included, depending upon the programming.The display 12 can be, for example, from 6 to 12 digits of the sevensegment type, with provision for decimal point and perhaps commas, aswell as two digits on the right hand side for exponents or scientificnotation. The display may comprise light emitting diodes (LED's), or agas discharge panel, or liquid crystal devices, for example. Thecalculator is a self-contained unit having a power supply in the form ofa battery or batteries within the housing 10, although an AC adapter maybe attached, as well as a battery charger.

Essentially all of the electronic circuits of the calculator system arecontained within a large-scale-integrated semiconductor chip which istypically packaged in a twenty-eight pin plastic package and mounted ona printed circuit board within the housing 10. The general organizationof the calculator system is seen in block diagram in FIG. 2, where thekeyboard 11 and display 12 are shown connected to the semiconductor chip15. Inputs to the chip are by four "K lines" 16 which are designated K1,K2, K4, K8, and a clear key input KC. Outputs from the chip includeeight segment outputs 17 which are connected to common segments of thedisplay 12. All like segments in each of the digits of the display areconnected together, so only eight segment outputs are needed. The digitsof the display 12 are driven by output lines 18 which are labelled D0 toD11, with digit drivers 19 being used to provide suitable voltage andcurrent levels for the particular display. Depending upon the number ofdigits in the display, the number of output lines 18 could be any numberup to thirteen. As will be seen, the number of digits in the display 12,the number of K lines 16 needed for the keyboard, and whether or nothardware clear key KC is used, as well as the desired number of pins forthe package, are optimized for a specific design. The lines 18 are alsoconnected to the matrix of key switches which makeup the keyboard 11.Assuming there are thirteen output lines 18, the matrix contains amaximum of 13 times 4 or 52 crosspoints so there are 52 possible keypositions (plus KC), not all of which are used for a given design. Aminimum function calculator with only a [X], [÷], [+], [-], [=], [C],[.], [0-9] keyboard would need only seventeen keys. Other input/outputpins for the chip 15 include a clear key input KC which can be used forthe "C" or clear function, a single voltage supply or Vdd line 20, aground or Vss pin 21, and two oscillator input and output pins 22 and 23which control the various options for the on-chip oscillator. Usuallythe pins 22 and 23 are connected together and a resistor connected toVdd from the pins for setting the frequency of an internal clockgenerator. More accuracy is provided by having a capacitor connected toground. To have one of the chips 15 synched by another, the pins 22 and23 are not connected, but the external synch from the output pin 23 ofthe other chip is connected to the input pin 22 of the driven chip. Atypical clock frequency is 500 KHz.

A standard 28 pin integrated circuit package may thus be employed for aneleven digit display. It is apparent that the 44 key switches, 11 digitsand eight segments per digit would require an excessive number of pinsif all input/output connections were made directly, so time-multiplexingof the keyboard and display input/output in the manner set forth inapplication Ser. No. 163,565 is vital. Twenty-four lines in the groups16, 17 and 18 provide the equivalent of 44 + 11 × 8 or 132 connections.

The chip 15 can provide a variety of functions as a general purposedigital processor. When used as a calculator as in FIGS. 1 and 2, theunit accepts keyboard inputs on the lines 16, performs functions such asadd, subtract, multiply, divide, square root, etc. on the input data asselected by operation keys, and outputs the results to the display 12.The electronic system needed to perform these functions is implementedin an MOS/LSI semiconductor chip containing over 8,800 MOS transistorson a wafer of silicon less than 0.2 × 0.2 inch in size. The chip can bemanufactured in volume for a unit cost of a few dollars, making possiblea calculator having very sophisticated functions yet selling in the 20or 30 dollar range.

The System Block Diagram

A block diagram of the system implemented on the chip 15 is shown inFIG. 3. The system is centered around a ROM (read-only-memory) 24 and aRAM (random-access-memory) 25. The ROM 24 contains 1024 instructionwords of 8 bits per word, and is used to store the program whichoperates the system. The RAM 25 contains 256 memory cells softwareorganized as four 16-digit groups with 4 bits per digit. Numerical dataentered by the keyboard is stored in the RAM 25, along with intermediateand final results of calculations, as well as status information or"flags", decimal point position and other working data. The RAMfunctions as the working registers of the calculator system, although itis not organized in a hardware sense as separate registers as would betrue if shift registers or the like were used for this purpose. The RAMis addressed by a word address on lines 26, i.e., one out of 16 wordlines in the RAM is selected, by means of a combined ROM and RAM wordaddress decode circuit 27. One of four "pages" of the RAM is selected byan address signal on two lines 28 applied to a RAM page address decoder29 in the RAM. For a given word address on lines 26 and page address onlines 28, four specific bits are accessed and read out on RAM I/O lines30, via input/output circuit 31, to RAM read lines 32. Alternatively,data is written into the RAM 25 via the input/output circuitry 31 andthe lines 30. The same 16 lines 26 used as RAM word address are alsoused to generate the display and keyboard scan on the lines 18; to thisend the lins 26 pass through the RAM 25 and are connected to outputregisters and buffers as will be explained.

The ROM 24 produces an eight bit instruction word on ROM output lines 33(the bits of the instruction word being labeled RO-R7) during eachinstruction cycle. The instruction is selected from 8192 bit locationsin the ROM, organized into 1024 words containing 8 bits each. The wordsare divided into 16 groups or pages of 64 words each. To address aninstruction in the ROM requires a one of-64 ROM word address on lines 34and a one-of-16 ROM page address on lines 35. The ROM word address onlines 34 is generated in the same decoder 27 as used to generate the RAMword address on lines 26. The ROM word address is a 6-bit addressproduced in a program counter 36 which is a six-stage shift registerthat may be updated after an instruction cycle or may have a 6-bitaddress loaded into it via lines 37 from ROM output lines 33 for a callor branch operation. The RAM and ROM word address decoder 27 receives a6-bit encoded address on lines 38 from decode data select unit 39 whichhas two inputs. The unit 39 receives a 4-bit address from RAM Y register40 via lines 41, and receives a 6-bit address from the program counter36 via lines 42, during each instruction cycle. A 6-bit subroutineregister 43 is associated with the program counter 36 to serve astemporary storage for the return word address during subroutineoperations. A 6-bit address is stored in the register 43, via lines 44when a call instruction is initiated so that this same address may beloaded back into the program counter 36 via lines 45 when execution ofthe subroutine which begins at the call location has been completed;this conserves instruction words and makes programming more flexible.The ROM page address on lines 35 is generated in a page address register46 which also has a buffer register 47 associated with it for subroutinepurposes. The register 46 will always contain the current page addressfor the ROM, and directly accesses the ROM page decoder. The bufferregister 47 is a multifunction buffer and temporary storage register,the contents of which can be the present ROM page address, an alternateROM page address, or the return page address during subroutineoperations. The program counter, subroutine register and ROM pageaddressing are all controlled by control circuitry 48 which receivesinputs from the ROM output lines 33 via lines 49. The control circuitry48 determines whether branch and call on "status" or subroutineoperations are performed, causes loading of an instruction word into theprogram counter and/or page address register, controls transfer of bitsto the subroutine or buffer registers and back, controls updating of theprogram counter, etc.

Numerical data and other information is operated upon in the system by abinary adder 50 which is a bit-parallel adder having a precharged carrycircuit, operating in binary with software BCD correction. The input tothe adder 50 is determined by an input selector 51 which receives 4-bitparallel inputs from several sources and selects from these what inputsare applied to the adder. First, the memory read or recall lines 32 fromthe RAM 25 provide one of the alternatives. Two registers receive theadder output, these being the "RAM Y" register 40 and an accumulator 52,and each of these output lines separately connected as inputs 53 and 54of the selector 51. A fourth input 55 receives an output from "CKB"logic as will be explained. Thus, the adder input is selected from thefollowing sources: data memory or RAM 25 on lines 32; accumulator 52 vialines 53; RAM Y register 40 via lines 54; constant, keyboard or "bit"information from CKB logic 56 on lines 55. Positive and negative inputsto the adder 50 on lines 57 and 58 are produced from the selectorcircuitry 51.

The output from the adder 50 is applied to either or both the RAM Yregister 40 and the accumulator 52 via lines 59. All of the operationsof the adder 50 and its input selector 51, etc., are controlled by adata path control PLA 60 which is responsive to the instruction word onlines 33 from the ROM. Control outputs 61 from the control PLA 60 areindicated by dotted lines. The 4-bit output from the accumulator can beapplied via lines 53 to an accumulator output buffer 62 and thus to asegment decoder 63 for output from the system. The segment decoder 63 isa programmable logic array like that disclosed in application Ser. No.163,565, and produces up to eight segment outputs on lines 64 which areapplied to a set of eight output buffers 65. The output arrangementcontains memory in the buffer 62 so that an output digit can be held formore than one machine cycle. Output is under control of the data controllogic PLA 60 which is responsive to the instruction word on lines 33from the ROM.

A status logic circuit 66 provides the function of examining for carryor compare from the adder 50, and determining whether to branch or call.To this end, inputs from the adder 50 via lines 67, and input from thecontrol PLA 60 via lines 61 are provided. The status logic 66 includes alatch which produces an output 69 to the output buffer register 62; thiscan be decoded out via segment decode 62 in many different ways. It canbe used to indicate decimal point DPT, and used to select two digit codesequences such as seven-segment or BCD out of the same PLA. For DPT, aBCD code of the desired DPT place would be stored in a location in RAM25, and this would be compared in adder 50 with the current D line 18being actuated which is defined in RAM Y register 40, and if they arethe same, status latch is set and DPT is shown on the display for thatdigit. Further, the status latch can be used to delineate between BCDdata out on certain lines 17, and control outputs on other lines 17.

A control circuit 70 determines what and when data is written into orstored in the RAM 25 via input/output control 31 and lines 30. This RAMwrite control 70 receives inputs from either the accumulator 52 vialines 53 or the CKB logic 56 via lines 55, and this circuit produces anoutput on lines 71 which go to the RAM I/O circuit 31. Selection of whatis written into the RAM is made by the instruction word on lines 33, viathe data path control PLA 60 and command lines 61. An important featureof the system is that constants or keyboard information, from CKB logic56, as well as the adder output via the accumulator, may be written intothe RAM, via the write control 70, and further the CKB logic 56 can beused to control the setting and resetting of bits in the RAM, via thewrite control 70.

The RAM page address into which data is written is determined by 2 bitsof the instruction word on lines 33, as applied via lines 72 to a RAMpage address register 73 and thus to lines 28 which select the RAM page.The RAM word or Y address is of course selected by the contents of RAM Yregister 40, select circuit 39 and decoder 27.

The four keyboard inputs 16 appear on lines 75, from which an input tothe CKB logic 56 is provided. In normal operation, a keyboard input goesvia CKB logic 56 to the accumulator 52 or RAM Y register 40, from whenceit is examined by software or ROM programming. In manufacture of thechips, a test mode is possible, where the keyboard input on lines 75 canbe entered directly into the ROM page buffer address register 46, aswill be explained. Also, during hardware clear using the KC input, the Klines can be entered into the page address register, or a K line can beused as an interrupt, in non-calculator applications.

Also included within the chip 15 is a clock oscillator and generator 80which generates internally a basic clock frequency of about 500 KHz orless, and from this produces five clocks 01 to 05 used throughout thesystem. A power-up-clear circuit 82 produces controls which clear thecalculator when the power is turned on. This may be also supplemented bythe KC input with an external capacitor.

The outputs 18 from the chip 15, used for keyboard and display scanning,are generated from the RAM word address on lines 26 by an outputregister 84 which is loaded under control on lines 61 as addressed byRAM word lines 26. The output from the register 84 is connected vialines 85 to a set of output buffers 86. Sixteen outputs are possible,but only perhaps 9 to 13 would be provided as outputs in a typicalcalculator design; for example 8 digits for mantissa, two for exponents,and two for annotators such as minus sign for mantissa and exponent.

It is important that the register 84 is a random access register, whereall bits are separately, independently, and mutually exclusivelyaddressed. In this embodiment, only 13 stages are provided in theregister 84, so only the first 13 of the 16 address lines 26 are used.When one of the 13 bits in the register 84 is addressed from decoder 27,this bit may be either set or reset as determined by controls 61 fromthe control PLA, i.e., from the current instruction word. The bit willremain set or reset until again specifically addressed and changed;meanwhile any or all of the other bits may be addressed and set or resetin any order. Thus, it is possible to have any combination of D registerbits either set or reset, providing 2¹³ or 8192 code combinations on theoutput lines 18. During power up or hardware clear, all the bits of theregister 84 are unconditionally reset.

Similar to the register 84, the other output register 62 is static inthat the contents once entered will remain until intentionally altered.The output register 62 functions as an output data buffer while theaccumulator 52 and status latch 66 are being manipulated to form thenext output. The output register 84 is a similar buffer for outputtingthe contents of the Y register 40, but has the additional feature ofbeing fully random access. The data sources for the Y register 40 arethe following: a 4-bit constant stored in the ROM 24 as part of aninstruction word; the accumulator 52 transferred to the Y register 40via the selector 51 and adder 50; and data directly from the RAM 25.Once data is in the Y register 40 it can be manipulated by additionalinstructions such as increment or decrement.

System Timing

A timing diagram for clock voltage waveforms used in the chip 15 of FIG.3 is shown in FIG. 4. The basic machine cycle, also referred to as aninstruction cycle, is an interval 90 made up of six intervals labeled91-96, each of which is nominally 2 or more microseconds in length, sothe machine cycle 90 is 12 microseconds or more. The phase 01 existsduring intervals 92 and 93, 02 during 95 and 96, 03 during 93, 94 and95, and 05 during interval 94, as seen in the drawing. The basic clock 0from which the clocks 01-05 are derived in the clock oscillatorgenerator 80 is shown for reference.

The Data Memory

Referring to FIG. 5, the RAM 25 and its input/output control circuitryis illustrated. The RAM 25 is composed of an array of 256 cells 100,each of which is a self-refreshing memory cell as seen in FIG. 21h, andas described in copending U.S. patent applications Ser. No. 454,349,filed Mar. 25, 1974, now U.S. Pat. No. 3,876,993, or Ser. No. 525,245filed herewith, both assigned to Texas Instruments Incorporated; suchapplications are incorporated herein by reference. The array isorganized 16 × 4 × 4, wherein sixteen address lines 26 provide the "RAMY" address function; that is, the four-bit indication usually containedin RAM Y register 40 is decoded in the decoder 27 to select one of thesixteen lines 26. These lines are labeled 26-0 to 26-15, representingthe A0 to A15 signals, 13 of which also correspond to the D0 to D12signals. The array of RAM 25 also includes 16 data input/output lines101, these being labeled 101-1 to 101-16; these are arranged in fourgroups of four, 101-1 to 101-4 being one group, etc. The 2-bit RAM Xaddress on lines 28 selects one-of-four of the lines 101-1 to 101-4,etc., in each group, and causes the four selected lines, one from eachgroup, to be connected to four input/output lines 30-1, 30-2, 30-4 and30-8 which correspond to the 1, 2, 4 and 8 lines for a 4-bit BCD code.Note that for simplicity only some of the cells 100 and representativeaddress and input/output lines are shown in FIG. 5; also, the 01 and 05lines needed for each cell in the array are not shown in the Figure.

The RAM page decoder 29 comprises four like groups of transistors 102which receive the true and inverted RAM X address signals from lines 28and enable paths such that only one of the lines 101 in each group offour is connected to the respective one of the lines 30. If a code "01"exists on lines 28 then lines 101-1, 101-5, 101-9 and 101-13 would beconnected to the lines 30-1, 30-2, 30-4 and 30-8 respectively. A code"11" would select lines 101-2, 101-14, etc.

The RAM I/O circuitry 31 comprises four like groups 31-1 . . . 31-8,each of which controls read or write for 1 bit. Each of the lines 30 isconnected to one of the write lines 71 through one of four seriestransistors 103 which are clocked on 03, so that data reaches the lines30 for write in during the significant interval 05, when it must existon the selected line 101. Phase 03 is wider than needed for this purposeas may be seen in FIG. 4. The lines 30 are shorted to Vss during 02 bydevices 104 which are clocked on 02, so that all I/O lines 101 are atVss or logic 1 at the beginning of each cycle. Data is read out ofsixteen selected cells 100 onto lines 101 during 01; then four selectedlines 101 are read onto the four lines 30-1 . . . 30-8 at this 01 time.For read out, the data goes through devices 105 which are clocked on 04during 01 time, into the gates of transistors 106. Transistors 107precharge the output lines 32-1 to 32-8 during 02, and the output linesare conditionally discharged via devices 106 during the next 04 (01)time. Thus the selected data will appear on read-out or recall lines32-1 . . . 32-8, valid during 04 (01) time interval 92. The gates oftransistors 106 will be shorted to Vss through devices 104 and 105during the interval 95 of 04, when 02 is also on.

The lines 101 are shorted to Vss during 02 by devices 108 duringintervals 95 and 96, since it is necessary for the lines to be at Vssbefore read-out which occurs during interval 92 of the next cycle. Allthe address lines 26 are at Vss during 02; this is implemented in theaddress decoder 27 such that an address or -Vdd exists on only one ofthe lines 26 only during 02, and at all other times all of the lines 26are at Vss. Only one address line 26 can be on at a given time.

The RAM write control 70 includes four like circuits 70-1 . . . 70-8,only two being seen in FIG. 5, which receive data inputs 53-1, 53-2,53-4 and 53-8 from the accumulator 52, and also receive four data orcontrol inputs 55-1 to 55-8 from the CKB logic 56. Transistors 109 areunder control of the voltage on a control line 110 when a "STO" commandappears on an output line 61-12 from data path control PLA 60. This canbe valid only when 02 is not at -Vdd as implemented in a gate 111.Transistors 112 are under control of the voltage on a control line 113when a "CKM" or CKB-to-memory command appears on another output line61-11 from PLA 60, also rendered valid only when 02 is not at -Vdd by agate 114. By these devices 109 and 112, the accumulator outputs 53 orthe CKB data outputs 55 can be inputs to the memory. The other CKBfunction is also implemented on the control 70. Output signals SETB andRSTB appearing on command lines 61-17 and 61-18 as outputs from thecontrol PLA 60 are applied to the gates of transistors 115 and 116 toproduce 1 and 0 (Vss and Vdd) voltages, respectively. Transistors 117 inseries with transistors 115 and 116, controlled by CKB outputs 55,provide the set and reset bit functions. Device 115 produces a ground orlogic 1 on input line 71 to the RAM if SETB is at -Vdd, for the one of 4bits selected by the CKB lines 55. Likewise, device 116 produces a logic0 on input line 71 if RSTB is at -Vdd, for the selected bit. Only one ofthe CKB lines 55 can be at -Vdd when CKB is functioning in the bit mode,the others are at ground which turns off transistors 117 for unselectedbits. This permits setting or resetting a specific bit in the RAM 25.This function is typically used for setting and resetting flags incalculator operation; a digit may be designated for flags, with one biteach as the add flag, minus flag, multiply flag and divide flag, forbookkeeping. Later, a specific flag bit is accessed via masking theadder inputs, again with CKB. Testing flags is by the compare functionin the adder. This mechanism simplifies the structure in that the samecontrols and select that are used in arithmetic functions are used inthe test bit functions.

The Adder

The binary adder 50 consists of a set of four parallel adder stages50-1, 50-2, 50-4 and 50-8 of conventional form. All four of the stagesare basically the same; two are shown in FIG. 6. Considering the stage50-1, each adder stage consists of a first complex gate 120 and a secondcomplex gate 121, a carry input 122 and a carry output 123. The complexgate 120 receives two inputs 57-1 and 58-1, sometimes identified asnegative and positive inputs, and produces an output on line 124 whichis the "exclusive or" or "equivalence" function of the inputs on 57-1and 58-1. A carry output is produced on the line 123 by firstprecharging the line 123 to a 0 or Vdd on 01, then conditionallydischarging when 01 goes to Vss, depending upon the output of a gate125; when both inputs 57-1 and 58-1 are 1, one generate condition forgenerating a carry is satisfied, so the output of gate 125 causes adevice 126 to be conductive after 01 ends, discharging line 123 to Vssor 1. A carry signal is produced on line 123 going to the next stage ifboth inputs 57-1 and 58-1 are 1, or if either of these is 1 and "carryin" on line 122 is 1, or if both inputs 57-1 and 58-1 are 1 and "carry"in on line 122 is 1, for all other situations, the line 123 remains at 0or -Vdd after 01 ends since neither the path through device 126 orthrough a device 127, nor the next stage, permits a discharge. The carryinput for the first bit comes from a CIN command from the control logic60 via a line 61-0; the line 122 is also precharged with 01. Carryoutput from the stage 50-8 appears on line 128, is gated on 03 andinverted, and provides a CAR8 signal on line 67-1 which goes to thestatus logic 66.

The adder 50 provides a "compare" function, wherein a COMP output isproduced on a line 67-2 which also goes to the status logic 66. Thissignal is produced on a line 239 which is precharged by 01 thenconditionally discharged on 01 when any of the devices 130 are turned onby the outputs 124 of the gates 120. Conditional discharge occurs ifline 124 goes to -Vdd, which occurs if the inputs to complex gate 120 at57-1 and 58-1 are not the same. When all of the inputs 57 are the sameas the inputs 58, COMP will be 1, otherwise 0.

Outputs from the adder stages 50-1, 50-2, etc., are produced on lines59-1, 59-2, 59-4 and 59-8, which are the outputs of the complex gates121. The gates 121 receive inputs 124 and carry in for that bit on lines122, etc. The gates 121 produce an "equivalence" function of the outputs124 and carry in. During 01, these outputs 59 are not valid, because thecarry circuit is being precharged. Carry is not valid, so the outputs 59are not valid, until after 01 ends. The adder output 59-1 is an input toeither the accumulator register stage 52-1 or the RAM Y register stage40-1, depending upon inputs 61-9 and 61-10 from the control PLA 60referred to as AUTA and AUTY. These controls go through inverting gates132 which also have 01 inputs, providing control lines 133 which can beat -Vdd only during 01.

The Adder Input Select

As shown in FIG. 6, the adder input select 51 includes four similar setsof complex gating arrangements 51-1, 51-2, 51-4 and 51-8 each consistingof complex NAND/NOR gates 135 and 136. The gate 135 receives controlinputs 61-4, 61-5, 61-7 and 61-8 from the control PLA 60, referred to as15TN, MTN, NATN and ATN, which determine whether the input 57-1 will beeither unconditional 1, or MEM1, or ACC1, or ACC1, respectively. Thedata from the RAM 25 appears on lines 32-1, 32-2, etc., from FIG. 5, andis referred to as MEM1, MEM2, etc. The data from the accumulator 52appears on lines 53-1 and 53-1' in true and inverted form, ACC1 and ACC1as inputs to the selector 51, so either the accumulator data or itscomplement may be the adder input. The inputs from the CKB logic 56 areprovided on CKB1, CKB1', et seq., lines 55-1, 55-1', etc., which bypassthe gates 135 and 136.

The CKB inputs are controlled by CKP and CKN through devices 137 and138. The control signals YTP and MTP on lines 61-1 and 61-2 selecteither RAMY from a line 139 or MEM1 from line 32-1 as the input 58-1 viagate 136.

The Accumulator and RAM Y Registers

FIGS. 6 also shows the accumulator register 52 which contains four likestages 52-1, 52-2, 52-4 and 52-8, as well as the RAM Y register whichhas four like stages 40-1 to 40-8. Each stage of these registers is aconventional one-stage shift register which recirculates upon itself viapaths 140, so bits entered into ACC or RAM Y will stay until new data isentered. The stages each consist of two inverters and two clockedtransfer devices, clocked on 02 then 01, of conventional form. Selectionof whether the adder outputs 59 go to ACC or RAM Y is made by AUTA andAUTY commands on lines 61-9 and 61-10, which produce controls on lines133 for devices 141. Data is valid at the outputs 59 from the adder 50after 01 goes to Vss, so the lines 133 do not go to -Vdd until after 01;this is the function of gates 132.

The outputs 41-1, 41-2, etc., and 139 from RAM Y are valid after 01ends. The true outputs 53-1, 53-2, etc., and inverted outputs 53-1',etc., from the accumulator are valid starting at 02.

The Data Path Control PLA

The control PLA 60 is shown in detail in FIG. 7. This device basicallyconsists of a programmable logic array of the type described in U.S.Pat. No. 3,702,985, Probesting et al., assigned to Texas InstrumentsIncorporated.

The current instruction word from the ROM 24 is applied in true andinverted form to the first section 60-1 of the PLA. These are theoutputs 33 from the ROM, corresponding to RO, RO, R1, R1, etc. The lines33, etc., are metal strips. Inverters 146, precharged on 02, produce theinverted RO, etc., signals. Thirty lines 146 in the first section 60-1are elongated P-diffused regions, and each is connected to Vdd through aseparate load device. All of the lines are clocked on 01. Betweenadjacent lines 146 is a Vss line, also a P-diffusion. The circlesrepresent thin oxide gate areas, so where a circle is present a line 146is connected to Vss when the overlying metal line 33 is at -Vdd,otherwise it stays at -Vdd. The coding of the PLA section 60-1 by gatesor circles is such that only one line 146 is actuated or at -Vdd for agiven instruction code on lines 33. The lines 146 become metal strips147 in the second section 60-2 of the PLA. Another set of 16 P-diffusedlines 148 underlie the metal strips 147, along with Vss lines (notshown). Again, the circles represent thin oxide gates under the metalstrips. The coding is such that for the one-of-30 lines 147 which isactuated, a selected set of lines 148 will be actuated with the proper 1or 0 logic level. The coding shown is for one example calculatoroperation. Both sections 60-1 and 60-2 are mask programmable inmanufacture, so many different instruction sets are possible. The lines148 contain the same commands as lines 61-0 to 61-15.

Note that for any instruction word where RO=1, a branch or call is beingimplemented, so none of the lines 147 will be actuated because noelements in the entire system controlled by lines 61 should beexercised. The RO line 33 in first section 60-1 has gates for everyline. All of the output lines 148 or 61-0 to 61-15 from the secondsection 60-2 are precharged to -Vdd by devices 149 clocked on 02; theselines 61-0 to 61-15 are diffused regions while within the section 60-2and then become metal strips for connection to the adder select, etc.,on other parts of the chip. A third section 60-3 of the control PLA 60is a simple decoder rather than a PLA. This decoder produces registerand bit set and reset commands, load or clear segment commands, and loador complement RAM X address commands, all on lines 61-16 to 61-23 whichare P-diffused regions. Loads, not shown, are connected to those lines.Particular ones of these lines are selected according to the gate codingand the current instruction word.

The Status Logic and Status Latch

In FIG. 8, the status circuitry 66 is shown in detail, including acomplex gate 66-1 for resetting status line 79, and a status latch 66-2.Status is normally a logic 1, so the machine normally branches, unlessstatus line 79 is reset to logic 0 or -Vdd. The latch is a conventionalcircuit with two clocked inverters and a feedback path. The output 69from the status latch 66-2 is connected to the output register 62. Thelatch may be set or reset, i.e., the line 79 connected to the latchinput via device 157 under control of an STSL command on line 61-15 fromthe control PLA 60, and 01. The output of status logic 66-1 (validbeginning at the last half of 02) is applied to device 157 via line 79,which is also connected to various gates in FIG. 11. Status logic 66-1is a dynamic OR gate clocked on 03, and produces an output under threesituations. One is "clear"; when the clear key is closed, KC occurs online 199, status signal is produced on line 79, meaning that the lineremains at -V for one instruction cycle. Another is the occurrance of aCAR8 signal on line 67-1 from the adder 50, FIG. 6; this, coupled with aC8 command on line 61-14 from the control PLA 60 generates "status" online 79. In either case the status latch can be set if STSL occurs onthe same instruction cycle. Thus, a carry output from the 8 bit of theadder can be used to generate status on line 79 and/or set status latch.Likewise, a COMP output from the adder 50 on line 67-2 can be used togenerate status if an NE command also occurs on line 61-13 from thecontrol PLA 60, so if the adder is used to compare two data inputs thenthe result can be used to generate status on line 79, and/or to set thestatus latch.

FIG. 8a shows the complex gate 66-1 in schematic diagram form ratherthan as a logic diagram. Note the output is precharged to -Vdd during03, and will conditionally discharge depending upon the logic inputsafter 03 goes to Vss, during which 02 is at -Vdd.

Generating the ROM Address

The ROM word and page addresses are generated in several alternativeways, employing the program counter 36, the subroutine register 43, theROM page address register 46 and buffer 47, as well as the controls 48and the ROM output itself on lines 33. These elements will now bedescribed.

The Program Counter

Referring now to FIG. 9, the program counter 36 includes eight stages36-0 to 36-7, each of which is a register stage having two inverters 160and 161, clocking being at 01, 02, with precharge on 03 for powersaving. Only six stages of the program counter are used in the normaloperation of the unit, these being stages 36-2 to 36-7 which receive theR2 to R7 ROM outputs from lines 33 via lines 37-3 to 37-7. The 6-bitaddress on R2 to R7 is gated into the stages 36-2 to 36-7 by devices 162when a BRNCAL "branch or call" signal appears on line 163 coming fromcontrols 48. This means that a successful branch or call operation isbeing performed so the part of the instruction code which defines thebranch address is loaded into the program counter by the path justdescribed.

The two extra stages 36-0 to 36-1 in the program counter unused inregular operation, are employed for test purposes. All eight bits of theROM output on lines 33, inverted and appearing as R0 to R7, may beloaded into all eight stages of the program counter via lines 37-0 to37-7 by gates 162 under control of a BRNCAL signal on line 163, toappear on nodes 164, from whence the eight-bit word is read out seriallyvia a terminal 165 during the next eight instruction cycles.

All of the stages 36-2 to 36-7 may be set to zero for power-up-clear bydevices 166 which are turned on when a PUC command appears on a line167, thus connecting a node 168 in each stage to Vdd. In this manner, aROM word address of 000000 is generated on lines 42.

The six outputs from the program counter stages 36-2 to 36-7 to the ROMaddress decoder are via six lines 42-0 to 42-5, representing PC0 to PC5signals. These are obtained at nodes 169 in each stage. Note that anaddress R2 to R7 on lines 33, when gated through devices 162, passesimmediately through nodes 164, inverters 161, and nodes 169, to lines42-0 to 42-5 without clocking delays.

The Subroutine Register

In FIG. 9, the subroutine register 43 comprises six identical stages43-2 to 43-7 corresponding to program counter stages 36-2 to 36-7. Eachsubroutine register stage includes two inverters 170 and 171, and afeedback loop 172, with gates clocked at 02 and 01. A bit, once entered,will recirculate continuously. When a "CLATCH" command is generated on aline 173 from control 48, the contents of the program counter 36 asappearing on nodes 174 will be loaded into the respective stages of thesubroutine register 43 via devices 175; this must occur on 02. Normally,the control line 173 is always on, so the contents of the programcounter as normally sampled into the subroutine register via devices 175on every machine cycle. But when a CALL is executed, the command is"don't load", so the last address is kept. The 6 bits thus loaded intothe subroutine register will thereafter continue to recirculateindividually within the stages 43-2 to 43-7, until such time as a "RETN"command appears on a line 176 from control 48. This would cause devices177 to load the 6 bits back into nodes 164 of the program counter stages36-2 to 36-7, and thence immediately through inverters 161 to nodes 169and output lines 42. At the same time, CLATCH goes negative so devices175 thereafter load address bits into the subroutine register untilanother CALL mode is reached.

The ROM Page Address Register and Buffer

Referring to FIG. 10, the ROM page address register 46 comprises fourstages 46-1, 46-2, 46-4 and 46-8, each of which includes a complex gate46' and an inverter 178, along with a recirculate path 179 and devicesclocked at 01 and 02. Output from the register 46 is via four lines35-1, 35-2, 35-4 and 35-8 from nodes 180, going to the ROM page decodein the ROM 24, valid during 02. For power-up-clear, all of the nodes 181may be connected to Vss by devices 182 under control of the PUC commandon line 167 as previously mentioned. This ultimately produces a 1111page address on lines 35. Input to the gates 46' can be from lines 183which are outputs from the buffer register 47, when a C4RX commandappears on a line 184 from control 48. Normally, however, the pageaddress is recirculating. The KC command, normally at Vss, blocks 02from driving line 185 to -Vdd.

The buffer register 47 includes four register stages 47-1 to 47-8, eachstage including a complex gate 47' (precharged at 03) and an inverter187, with transfer gates clocked at 01 and 02, and a recirculate path188. As before, a power-up-clear command on line 167 will connect allnodes 189 to Vss via devices 190, to clear the buffer register.

Inputs to the buffer register stages 47-1 to 47-8 via complex gates 47'may be from several sources. First, the ROM outputs R4, R5, R6, R7 onlines 33 may be loaded into the buffer via lines 78-1 to 78-8 when aC1RX command is produced on line 191 from the controls 48 (aninstruction word of 0001XXX), both of these inputs to the gates 47'being gated in on 01. Second, the output from the ROM page addressregister 46, appearing on lines 192, will be the input to gates 47' whena C2RX command appears on line 193 from control 48, gated on 01; thisoccurs for a CALL when status is at logic 1. Third, the buffer stagesmay be caused to recirculate upon themselves by loops 188 when a C3RXcommand appears on line 194 from control 48; this occurs whenever C1RXor C2RX are both at Vss, i.e., the register 47 usually recirculatesexcept when an address is being loaded from R4-R7, or a successful CALLis being implemented. In the test mode A KC signal on line 199 can causethe keyboard input lines K1 to K8 to be input to the gates 46' viatransfer devices 196 and lines 192; this is used for test or infunctions other than calculator functions. Also, -Vdd on the clear keyline KC produces an input to gates 197 which are parts of the complexgates 47', to essentially disable any control by the C2RX command online 193, breaking the path that loads the outputs 35 into 47 via lines192; this provides a hardware clear function and other alternatives.

Generally, the registers 46 and 47 contain the same data, meaningaddresses are being used which are on the same "page" in the ROM. Allthe branches are to the same page. However, to go to a different page,i.e., a long branch, a new page address is loaded in from R4-R7 toregister 47. This results in the current address being in register 46and on lines 35, and the new page address to go in register 47. If thebranch is true or status condition satisfied, register 47 is transferredto register 46 and thus to lines 35. At this point, the same data isagain in registers 46 and 47, so the machine is set up to do shortbranches again on the new page. If a CALL is executed, register 47 istransferred to register 46, and vice versa. Of course, if the call is onthe same page, the data is the same in each register anyway. But if itis a long call, to a different page, then register 47 functions to storethe address of the page existing at the time the CALL is initiated. So,when a return is executed, register 47 is transferred to register 46,the two registers again have the same data, and the machine is at theinitial address, set up for short branches.

The Address Controls

Referring to FIG. 11, the control 48 for the ROM addressing circuitryincludes several separate complex gates 48-1, 48-2, etc., for generatingthe various commands. The gate 48-1 produces the C1RX command on line191 in response to the presence of R0, R1, R2 and R3 on lines 33, alongwith the KC input on a line 199 being at Vss. This loads in a new pagefrom R4-R7 on lines 33 for a long branch or call. A gate 48-2 producesthe C3RX command on line 193, in response to the presence of R0, R1 onlines 33, KC on line 199, and a status signal on line 79 from statuslogic 66; all these must be at Vss for C3RX to be at -Vdd. This meansthat a 11XXXXXX instruction word is on lines 33 and status is atlogic 1. This is a CALL. The KC input to gates 48-1, 48-2 and 48-3functions to disable all these gates when the clear key is pressed. Agate 48-3 produces the C3RX command on the line 194 in response to KC online 199 and the C1RX and C2RX commands at the outputs of gates 48-1 and48-2 all being at Vss. This says recirculate the register 47 via lines188, i.e., save the address in the buffer register. A gate 48-4 producesthe C4RX command on the line 184 as a function of status on line 79, ROfrom the lines 33, the RETN signal on line 176, and a signal derivedfrom CLATCH, appearing on a line 200. Whenever a return is executed,C4RX should go to Vss, so register 47 can be loaded into register 46 vialines 183. The RETN command 178 is produced by a gate 48-5 in responseto R0, R1, R2, R3, R4, R5, R6, R7 on lines 33; that is, an instructioncode of 00001111 results in a RETN command, recalling the address in thesubroutine register 43 to the program counter 36 and thus to the lines42 going to the decode select 39, as well as loading register 47 intoregister 46. The CLATCH command is produced from a complex gate 48-6,which is responsive to status on line 79, R0 and R1 from lines 33, RETNon line 176, KC on line 199, and the power-up-clear signal PUC on line167. A function of CLATCH is to disable the path 183 from register 47 toregister 46 when a CALL is executed. This is done by line 200 going togate 48-4, which is also responsive to R0 and status being at Vss. Byline 184, and line 185, the recirculate path 179 for register 46 isenabled in gates 46' while the path 183 is disabled. R0 and status being1 are a successful branch or call, and would cause transfer of register47 to register 46, but CLATCH says don't do it. CLATCH is normally inthe non-CALL mode, saying that the machine is not calling but isbranching. If R0, R1 and status are 1 into gate 48-6, it means a validCALL, so the latch is set into CALL mode. The RETN instruction saysleave the CALL mode, and reset the latch. KC or PUC also reset thelatch. The inverter and gate between node 201 and the line 200, alongwith the gate 48-6, provide a feedback loop and thus a latch function,so that when CLATCH is produced it will subsist until return RETN,hardware clear KC, or power-up-clear PUC occurs. The BRNCAL command online 163 is produced in a gate 48-7, which is responsive to R0 andstatus. The gate 48-7 looks for a successful branch or call; the wordaddress transfer is always implemented when R0 is 1 and status is 1.

In the test mode, the KC and K2 inputs to gate 48-7 are functional.Normally KC is negative so K2 is out of the circuit. If KC is at Vss,then K2 can control BRNCAL. In test mode, after serially loading in anaddress on the K1 line, then if K2 is grounded a BRNCAL command isproduced. This forces all eight ROM bits from lines 33 into the programcounter 36 via devices 162 in FIG. 9, from whence the bits aretransferred out via line 165 for testing. BRNCAL is grounded on 02 ingate 48-7, so it is valid during 02.

The Keyboard Input

Also shown in FIG. 11 are the keyboard input lines 75 which come fromthe inputs 16. Schmidt trigger circuits 205 are used between the lines16 and the lines 75 to impose a threshold and hysteresis effect. Whilereferred to as a keyboard input, and used as such for calculators, it isunderstood that BCD or binary data may be entered directly into thelines 16 from any source when the digital processor chip of theinvention is used for other purposes. Note that true data is a 1 or Vsslevel, and at other times the lines 16 and thus lines 75 will be held at0 or Vdd by depletion load devices L. The KC line 206, used for hardwareclear or the "clear" key in calculator applications, is connectedthrough an inverter to the KC line 199; when the clear key is up, KCwill be at Vss or 1, and when the clear key is depressed, line 206 willbe grounded and line 199 will go to -Vdd. An external capacitor 207 maybe used with the chip to provide a delay and smoothing or debouncefunction for the KC input.

Generally, in using the processor chip as a calculator, numerical datais not entered via the keyboard inputs in the form of numerical data;that is, when a 7 key is depressed, a BCD 7 or 0111 is not generated onthe K lines, but instead typically a sequence of programming steps isemployed to detect that a key is down, then store the K line informationin the accumulator 52 while the identity of the line 18 which isactuated is stored in the Y register 40. This data may then be used toidentify the key by software and enter a BCD number in the RAM 25 orexecute an operation.

An advantage of this input system is that numbers and operations may beintermixed on the K lines, and the numbers need not be in numericalorder. Also, two keys might be pushed at the same time, and one may berejected by software. Further fixed switches as for DPT position may beintermixed with momentary switches. None of these could be done in priormachines.

Except for testing mode, the keyboard inputs go to the CKB logic 56only. From there, the keyboard can be loaded into the accumulator or RAMY registers.

The Control-Keyboard-Bit Logic

The CKB logic 56 shown in FIG. 12 consists of four identical complexgates 56-1, 56-2, 56-4 and 56-8 which produce the CKB1 to CKB8 outputson lines 55-1 to 55-8. The CKB outputs are applied to the adder inputselect 51 and to the RAM Write control 70, as explained. Each of thefour complex gates 56-1 to 56-8 contains three separate gatingarrangements 210, 211 and 212, each of which will produce a CKB outputunder certain conditions, dependent upon the current instruction word onlines 33. The gating arrangements 211, in each case, receive R0, R1, R2,R3, R4 from lines 33 into AND gate 213, and either K1, K2, K4 or K8 fromlines 75-1 to 75-8 into AND gate 214; this serves to place the keyboardor external data on the CKB lines 55, when the instruction word is00001XXX. The gating arrangements 210 function in setting and resettingbits in the RAM 25, and receive R0, R1, R2 and R3 from lines 33 into ANDgate 216, so this part will be responsive to an instruction word0011XXXX, while the remaining parts of the gates 210 are responsive totwo of the R6, R6, R7 or R7 lines via OR gates 217 so that only one ofthe four gates 56-1 to 56-8 will produce a CKB output. This serves toselect one of the four bits for a bit operation. The gating arrangements212 include an AND gate 218 in each case, responsive to R2, R3, R4 fromlines 33. The output of gate 218 is OR'ed with R1 in gate 219, which inturn is connected to AND gate 220 along with R0 and either R4, R5, R6 orR7. Thus, complex gates 212 serve to place all 4 bits R4, R5, R6 and R7on the CKB outputs 55 when the instruction code is 01XXXXXX and any oneor more of R2, R3 or R4 is a 0. For some constant operations, R4 or thefirst bit in the constant field is always a 1 -- this is a necessarylimitation on the constants which may be employed in this case. R1 isactually a don't care bit, if R2-R4 are 0, in that code of 00000XXX alsoapplies the constant field R4-R7 to the CKB lines 55.

Referring to FIG. 12a, one of the complex gates 56 is shown, this beinggate 56-8. The other gates 56-1, 56-2, 56-4 would be the same except forchanges in the R6, R7 and K inputs as shown in FIG. 12. On 02, theoutput line 55-8 is precharged to -Vdd through device 222, then during01 of the next cycle the output line 55-8 is conditionally dischargedvia the gate arrangements 210, 211 and 212, and device 223. It is seenthat if the instruction code on lines 33 is 0011XXXX, gate 210 will becontrolling because gate 212 will be shorted by R1 and R2, R3 while gate211 will be shorted by R2 and R3. Thus, for 0011XXXX, one of the fourCKB gates 56 will be selected by gates 217 which receive combinations ofR6, R6, R7, R7. If the instruction on lines 33 is 00001XXX, gate 211will be controlling because gate 210 is shorted by R2, R3, while gate212 is shorted by R1, R4, so that K8 will determine whether line 55-8 isshorted to ground. If the instruction on lines 33 is 01XXXXXX, the gate212 is controlling because gates 210 and 211 are shorted by R1, so R7(or R4, R5 or R6 in the other gates 56) will determine discharge of line55-8. Gate 212 also controls if the code is 00000XXX, because gate 210is shorted by R2, R3 and gate 211 is shorted by R4, while gate 219 isnot conducting because R2, R3 and R4 are all 1's.

The overall function of the CKB logic 56 is thus seen to be threefold.First, a constant appearing in a field of the instruction code may beapplied to the lines 55. Second, the keyboard or external inputs onlines 75 may be applied to the lines 55. Third, one of the four lines 55may be selected, as for addressing one of four bits of a digit in theRAM 25. All of these functions are under control of the currentinstruction word.

The RAM Page Address

In FIG. 13, the RAM page address register 73 is shown. The RAM pageaddress consists of two bits, RAX0 and RAX1, which appear on lines 28.The register consists of two identical stages 73-0 and 73-1, each ofwhich has an input 225, two inverters 226, and two separate feedbackpaths 227 and 228. Each stage is thus a recirculating register, clockedon 01 and 02. A two-bit RAM page address may be loaded into the inputs225, if devices 230 are turned on by a LDRAX or "load RAM X" command online 61-23 from the control PLA 60. The address, once loaded, willrecirculate indefinately via path 228. The RAM X address in the registeris complemented when devices 231 are turned on by COMRAX command on line61-22 from the control PLA 60 if it is a 0 or -Vdd. This causesrecirculation via paths 227, and the address will be complemented. WhenCOMRAX is a 1, the bits will recirculate via paths 228, and the addresswill remain the same.

The RAM page address is contained in the 2-bit X register 73 which isused to directly address the RAM page decoder 29 via lines 28. Theregister 73 may be modified in two ways. First, R6 and R7, from the ROM24 as part of the instruction word can be loaded, as described. Second,the address stored in the register 73 can be complemented bit for bit.No other mechanism including power-up-clear and hardware clear have anyaffect on the X register 73. Modifications that do occur in the register73 are not valid until the next instruction cycle.

The ROM and ROM Page Address Decoder

Referring to FIG. 14, the ROM 24 and the ROM page decoder are shown. TheROM consists of an array of X lines 240 which are elongated P-diffusionsin the semiconductor substrate, and Y lines 241 which are metal stripsover a field oxide coating on the substrate, made in conventionalmanner. Sixty-four of the Y lines are provided in the array, althoughonly a few are seen in FIG. 14, and 128 X lines. The ROM is of thevirtual ground type, and so only one ground line 242 is needed for eacheight X lines 240; interior ground lines are shared with adjacentgroups, so actually only nine ground lines are needed rather than 16.Virtual ground ROM's are disclosed in copending U.S. patent applicationsSer. No. 396,901, filed Sept. 13, 1973, now U.S. Pat. No. 3,916,169, andSer. No. 400,471, filed Sept. 24, 1973, now U.S. Pat. No. 3,934,233assigned to Texas Instruments. A data bit is formed between adjacentones of the lines 240, or between a line 240 and a ground line 242, bymeans of thin oxide areas 243 as set forth in U.S. Pat. No. 3,541,543,assigned to Texas Instruments. A pattern of the thin oxide areas 243define the 1 or 0 stored for each data bit, as they will each define thepresence or absence of an MOS transistor. The ROM contains 8192 data bitlocations or potential locations for the thin oxide areas 243. Thelocations are organized as 1024 words containing 8 bits each. The 8 bitsexit from the ROM on eight lines 33 (only one of which is shown in FIG.14) which correspond to bits R0 to R7 of the instruction word. The 1024words are divided into 16 groups or pages of 64 words each.

The page decoder consists of 16 arrays 244 of transistors 245. Only twoarrays 244 are shown, but there are 16 exactly alike. Each arraycontains only 14 transistors 245, and one transistor 246, which is agreat improvement over decoders for prior virtual ground ROM's. Thedecoder receives the 4 bit ROM page address on four lines 35-1 to 35-8,from the ROM page address register 46 of FIG. 10. Four input/prechargecircuits 247, all alike, receive the ROM page address bit clocked in on02 by devices 248. Inverters 249 provide for true and complement, soeight address lines 250 run the entire width of the ROM, through allsixteen of the arrays 244. These lines 250 provide X1, X1, X2, X2, X4and X4 inputs to the gates of transistors 245, and X8 and X8 inputs tothe gates of transistors 246. The selected lines 250 are charged on 02via devices 251, with bootstrapping by gated capacitors 252. An outputcircuit 253 connects each of the pairs of arrays 244 to one of the lines33, so there are eight of the circuits 253, all alike. Adjacent arrayseach have output lines 254 and 255, which are also X lines 240 in theROM array; the X8, X8 address bit selects only one of these output linesvia transistors 246. The one selected is connected to the input of aninverter 256, to ground the output line 33 via device 257 if theselected one of the lines 254, 255 is at Vss when 02 occurs, or toconnect the output line 33 to -Vdd (through 02) via device 258 if theselected one of the lines 254, 255 is at -V when 02 occurs. A gatedcapacitor 259 serves to bootstrap the output to a high level. The pageaddress selects one of eight lines 240 in each group of eight by thetransistors 245 in each array 244; the 1, 2 and 4 bits, i.e., X1, X1,X2, X2, X4, X4 lines are actuated in a pattern which connects one X line240 to ground line 242 and the next adjacent X line 240 to line 254 or255. For example, a ROM page address of 1010 (listed X1, X2, X4, X8)connects line 240a to ground line 242 via devices 245a and 245b, andconnects line 240b to output line 254 via device 245c, while the device246 on the X8 line connects line 254 to the node 260 and thus to theoutput. Any thin oxide gate 243a between lines 240a and 240b will thusbe determinative, for the particular Y line 241 selected by the Y decode27 to be later described.

An important feature of the ROM is the manner of precharging the lines240. All of these lines 240 are connected to a common line 262 bydevices 263 which are clocked on 01. The common line 262 is connected tothe -Vdd supply 264 by two enhancement mode MOS transistors 265, so thatthe line 262 charges to -(Vdd - 2Vt), where Vt is a threshold voltagefor the devices 265. Typically, Vdd is 15.0 volts and Vt is 2.0 volts.So, the lines 240 charge toward a lower voltage, meaning that the lineswill be precharged fast and will discharge fast, compared to theperformance if the lines are precharged to Vdd.

The ROM/RAM Word Decoder

Referring to FIG. 15, the word decoder 27 for the ROM 24 and RAM 25 isshown in detail, along with the data select circuit 39. The decoder 27receives a twelve line address (six bits and their complements) on lines38, and selects one of 64 output lines 34 for the ROM or one of 16 lines26 for the RAM. The lines 34 are the metal stripes or Y lines 241 in theROM. The select circuit 39 receives a four-bit RAM Y address on fourlines 41-1 to 41-8 from the RAM Y register 40, gated in on 02 by devices270. The circuit also receives the six-bit program counter output 42 onlines 42-0 to 42-5, gated in on 01 by devices 271. During every machinecycle, a ROM address is delivered on 01 and a RAM address on 02. Sincethe RAM Y address is only 4 bits (2⁴ = 16), while the ROM address is 6bits (2⁶ = 64), the extra bits are connected to Vss and Vdd at points272 and 273, respectively, for the RAM address. With inverters 274,trues and complements are provided to the decoder on twelve lines 280(same as lines 38), these being labelled Y1, Y1 . . . Y6, Y6. The lines280 are metal strips, overlying P-diffused lines 281, to form an arraysimilar to a ROM. Thin oxide areas are provided in selected bitpositions under the lines 280 to create MOS transistors 280' betweenadjacent ones of the lines 281. A given 6-bit code selects one of thelines 281. All of the lines 281 are connected to the gates of devices282 on 01 via devices 283. Gated capacitors 284 serve to bootstrap thegate voltage on 282 to a higher level. The lines 241 are all at grounduntil one is driven negative during 02 from line 285, due to one of thetransistors 282 having had its gate driven negative during 01. The lines281 are charged by 04 twice during each machine cycle. 04 is applied tolines 281 from line 286 via devices 287 and 288. During the first partof 01, all of the lines 281 and gates of devices 282 charge negativefrom 04, then during the last half of 01, 04 goes to ground and all butone of the lines 281 and gates of devides 282 discharge back to ground,depending on the pattern of thin oxide areas connecting lines 281together and depending on which ones of the lines 280 are negative.Devices 289 and 290 select alternate paths for discharging of the lines281. These devices 289 and 290 are gated by Y6 and Y6, so one willalways be on and the other off, during 01 and 02. The lines 281 alsocharge negative from 04 during interval 95, the first half of 02, thenduring the last half of 02 all but one discharges to ground into the 04source.

The output from the decoder 27 to the lines 26 occurs on 02, via devices292, through which sixteen of the sixty-four lines 281 are connected togates 294 of devices 295 in address output circuits 300, of which thereare sixteen identical circuits -- only four are shown. The selected RAMaddress line 26 is driven to -V during 02 from line 301, by device 295.Bootstrap-gated capacitor 295' assures a high negative level on selectedline 26. The unselected lines 26 are held at ground by a zero-keepingcircuit including devices 302, 303 and 304. During 02, while gate 294 isbeing charged for the one selected output, the device 304 conducts anddrives the gate 305 negative, turning on transistor 302 and thusconnecting all the lines 26 to Vss line 306. Then, when 02 goes toground, and 02 goes negative, node 307 of the selected address line 26starts negative, turning on device 303 and discharging node 305, thusdisconnecting the selected address line from ground. The unselectedaddress lines will stay at ground because node 305 will remain negative,keeping device 302 on. The effect of this output circuitry 300 is thatlines 26 will all be at ground during 02, and during 02 they will all beat ground except the selected one which will be at -Vdd.

The D Output Register

Turning now to FIG. 16, the output register 84 and output buffers 86 areshown in detail. This register consists of 13 identical stages 310, onlythree being illustrated. Each stage 310 is a self-refreshing RAM cellgenerally the same as used in the RAM 25, but with added controls. Thecell includes five transistors 311, 312, 313, 314 and 315. Thecapacitance of node 316 and the capacitance of the gate 317 oftransistor 311 are important. If a negative voltage is stored at node316, it will charge gate 317 during 05 via device 314. Then during 01,the negative voltage on gate 317 turns device 311 on, and device 312will be on, so node 316 will charge more negative, refreshing the storedcharge. If the node 316 is at Vss, gate 317 will not be charged during05, device 311 will not turn on during 01, so node 316 will remain atVss. Input to the node 316 is via device 313 which is turned on or offby one of the address lines 26. All of the devices 313 of the 13 cells310 are connected to a line 320, which is grounded during 02 by device321. Lines 61-16 and 61-17 receive SETR and RSTR commands from controlPLA 60, which connects the line 320 to ground or Vdd, respectively, viadevices 322 and 323. The nodes 315 are forced to -Vdd uponpower-up-clear or by the clear key via command line 324 upon which KC +PUC is applied from clear circuit 82. A negative voltage on line 324turns on device 325, applying a 0 or -Vdd to node 316. All of the cells310 will remain in this 0 state until a SETR command occurs and one ofthe lines 26 goes to -V, which occurs during 02. Only one of the cells310 can be set during one instruction cycle because only one RAM Yaddress line 26 goes negative. Once set to 1 or Vss, a cell will remainin that condition until specifically addressed and reset by actuatingRSTR command and addressing the cell by a line 26. The stages 84-0 to84-12 can be set and reset in any order, and several or all can be inthe set condition at the same time. For example, if it is desired totest for "any key down", all of the outputs 18 may be actuated bysetting all of the stages 84 (requiring one instruction cycle for eachstage) then the K lines would be read in and tested. Also, leading zerosuppression may be implemented by various routines because all D outputsneed not be actuated, and they may be actuated MSD to LSD, or LSD toMSD.

The output buffers 86 function to provide either Vdd or ground potentialto the terminals 18, according to the bits stored in the various stagesof the register 84. The circuitry shown is adapted to assure fullvoltage swing.

The Accumulator Output Register and Segment Decoder

In FIG. 17, the accumulator and status output register 62 is shown indetail along with the segment decoder PLA 63 and the output buffers 65.The register 62 consists of five identical recirculating register stages62-1, etc., each of which includes a NAND gate 330, an inverter 331, anda recirculate path 332. The stages are clocked at 03 and 02 by lines 333and 334. Input data is applied to stages 62-1 to 62-8 from theaccumulator output lines ACC1 to ACC8 (53-1 to 53-8) from FIG. 6. Inputdata is applied to the status buffer 62-5 from the status latch outputline 69 of FIG. 8. These inputs are loaded via devices 335 upon theoccurrance of a LODS command on line 61-20 from the control PLA 60. Allof the stages of the register 62 may be cleared by a CLRS command online 61-21 from the control PLA 60, which is an input to all of thegates 330. Also, the stages of the register 62 are cleared, that iszeros are loaded, by a KC + PUC command on line 324. True and complementoutputs from the states 62-1 to 62-5 are applied by A1, A1, A2, A2 . . .S, S lines 336 to 10 inputs to the first section 63-1 of the PLA 63,which causes one of twenty lines 63-2 to be actuated in the usual mannerof coding PLA's. The second section 63-3 of the PLA is coded to actuateone or more of the lines 64 for inputs on the lines 63-2. The PLA 63 maybe coded to convert the BCD information on the accumulator output tostandard seven-segment display drive signals for typical calculatoroperation, or BCD may be sent out on four of the lines 64, or any otherdesired code. Decimal point placement may be by the status latch outputon S8.

The eight output buffers 65-1 to 65-8 are all alike -- only two areshown in FIG. 17. These buffers function to apply Vss or -Vdd to theoutput terminals 17 for driving the segments of the display or otheroutput such as data lines or a printer.

The Power-Up-Clear Circuit

In FIG. 18, a circuit is shown for generating power-up-clear command PUCon line 167 of FIGS. 9 and 10, and generating the "hardware clear orpower-up-clear" command KC + PUC on line 324 of FIG. 17. An OR gate 338receives the clear key signal from KC on line 199 and an inverter. PUCis generated by a latch 340 and a capacitor 341. When power is firstturned on, the capacitor 341 is not yet charged, and the input 342 isessentially at ground, so latch 340 is in one state, producing an outputvia line 343 to produce PUC on line 167 and KC + PUC on line 324. Afterthe capacitor has charged, the latch 340 flips, and PUC goes back toground so the calculator can operate in its usual mode. Feedback loop344 assures that the capacitor discharges, or that the latch 340 is inthe proper state, when power comes on. If an external capacitor is used,KC inverted, on line 345, serves to stretch PUC. The remainder of thecircuitry is for testing the chip. The output 165 of the last stage 36-0of the program counter 36 is connected to the device 346, which isturned on by KC on line 199. The output of the device 346 is connectedby line 347 to the input of the S8 output buffer 65-8. So, when KC isnegative, the contents of the program counter 36 can be read outserially on a terminal 17-8, via buffer 65-8. When KC is at ground,device 348 is turned on, and line 64-8 is connected to the S8 outputbuffer for the usual operating mode.

The Program Counter Feedback

Referring to FIG. 19, a feedback circuit for the program counter of FIG.9 is illustrated. This logic arrangement examines the six individualoutputs 42-0 to 42-5 of the program counter 36 and determines whether a1 or 0 is to be fed into the first stage of the program counter via line350. An exclusive OR circuit 351 examines lines 42-4 and 42-5 which arethe outputs of the last two stages of the counter 36, and generates anequivalence; if both are 0 or both 1, a 1 is fed back to input 350, andif they are different, then a 0 is fed back. This permits a count up to63 in a random manner, but some means must be provided to break out of asituation of all ones in the shift register 36. With all ones, the termfed back would be 1, and the counter would remain at all ones. To avoidthis, the gate 352 is responsive to 012345 and forces a count of 111111,where the counter would be stuck, but AND gates 353 and 354 are togetherresponsive to 012345, forcing a 0 as the next feedback. This arrangementcauses the six stage shift register to count to 64 in a psuedorandommanner, ie., in a set repetitive order but not in regular order. Thegating arrangement 355 is for testing; when KC appears on line from FIG.11, the usual path from gate 351 is broken, and the K1 input on line75-1 is fed serially into the program counter input 350.

The Clock Generator

Referring to FIG. 20, a block diagram of the clock generator 80 isillustrated. The clock generator consists of three conventional counterstages 360, each of which is clocked by 0 and 0 which are obtained froma clock oscillator 361. The clock 0, at a frequency of about 500 KHz,may be synched directly from the external pin 22, or the external pins22 and 23 may be tied together and to -Vdd through a resistor 362 whichsets the frequency. The frequency may be set more precisely by using asmaller resistor and a capacitor 363 connected to Vss. In any event, theoscillator 361 may be of various forms. To generate the six intervals91-96 of FIG. 4, from the clock 0, counter stages are connected to countto six in conventional manner, using a feedback circuit 364. A decoder365 selects from the three output puts 366 from the counter,representing the six distinct states of the counter, to produce 01, 02,03 and 05 on output lines 367, and these are inverted to produce 01, 02,03 and 05 on outputs 388, to be used throughout the system. To generate04, the output 367 for 01 and 02 are connected to an OR gate 369, theoutput of which is delayed one interval by one counter stage 370,producing 04. The inverted 04 output provides 04 on line 371.

Details of Logic Blocks

In FIG. 21a to 21j, the logic gates, inverters, etc. which are used inthe system of FIGS. 3 and 5-20 are shown in detail. Note that all of theinverters are of the ion implanted depletion load type, which minimizespower consumption. The gates use either depletion loads, or gated loads,or are of the precharge type, again for power savings.

The Instruction Set

The 8-bit instruction words contained in the ROM 24 and read out ontothe lines 33 are of the format shown in FIG. 22, where block 380represents a word containing eight bits R0 to R7. This word may beconsidered as having certain fields and subfields, which are differentfor various functions. The R0 bit always distinguishes between branch orcall (logic 1) and operation (logic 0); this is the OP1 field. Theinstruction set has four basic formats I, II, III and IV, and the fieldOP1 appears in all. Format I is for branches or calls, and includes afield CB at R1 which distinguishes between the two, along with a field Wat R2 to R7 which is a 6-bit address for the location of the branch orcall. Format II is that of instructions involving constants of 4 bitscontained in field C at R4 to R7; here the 3-bit OP2 field at R1 to R3defines the operation performed with the constant. Format III is for bitand RAM page operation, where field B is the bit or address, field Fdefines the operation, and field OP3 is characteristic of the 011 codefor bit or RAM page operations. Format IV is for arithmetic or specialinstructions defined by fields OP3 and A.

A Karnaugh map of the general classes of instructions is shown in FIG.23. An 8-bit instruction word permits 2⁸ or 256 possible combinations orunique instructions. One fourth of these, the 64 in the upper left 11quadrant, represent 64 possible CALL operations. Another one-fourth, the10 quadrant, represent 64 possible branch operations, i.e., each being abranch to one of 64 possible ROM locations. The lower left 01 quadrantcontains 64 possibilities for constant operations, with each quadrant ofthis containing 16 possible constants in the 4-bit constant field C. The00 quadrant, lower right, contains 16 possible page addresses for longcalls or long branches in the C field of the 0001 portion, and contains16 "bit" and RAM page operations in the 0011 portion. All of thearithmetic and special instructions are contained in the 32possibilities in the 0010 and 0000 parts.

A detailed description of one instruction set is set forth in theattached Table. Other instruction sets are possible by reprogramming thecontrol PLA and the ROM. The one described in the Table is useful forcalculator functions.

Note that the mnemonics for the various instructions in the instructionset are identical with most of the lines 147 and 61-16 to 61-23 of thecontrol PLA of FIG. 7.

It will be noted that operation of the program counter 36 and thesubroutine register 43 depends on the mode (or machine state) of thesystem. Two states are possible, the normal state and the CALL statewhich signifies entry into a subroutine. Machine state is determined bythe status of the CALL latch 201 which is controlled by successful CALLor RETURN instructions.

At the beginning of each instruction cycle during which the machine isin the normal mode of operation, the work address present in the programcounter 36 is updated via the circuit of FIG. 19 to generate the nextROM word address and this next ROM address is unconditionally stored inthe subroutine register 43. Upon execution of a successful CALLinstruction, the machine enters the CALL state preventing further datatransfer into the subroutine register 43. The contents of the subroutineregister 43 are not held at the word address of the CALL instruction,but instead at the word address of the next sequential instruction.

Executing a RETURN instruction will return the machine to the normalstate and transfer the contents of the subroutine register 43 into theprogram counter 36, thereby returning to the proper word address.

The program counter 36 is not affected by the machine state or CLATCH.The program counter will generate the next word address everyinstruction cycle unless the contents are altered by the execution of asuccessful CALL, a successful BRANCH or a RETURN instruction.

The machine state will alter the function of the ROM page bufferregister 47. During the normal mode, the register 47 serves as a sourcefor new page information when executing a successful CALL or a BRANCH. Asuccessful BRANCH when executed in the normal mode will always copy thecontents of the register 47 into the ROM page address register 46.Therefore, unless the contents of the register 47 are modified, any andall subsequent successful branches will be within the same page.BRANCHES of this type are called short branches. To branch to adifferent page, a long branch, the contents of the register 47 must bemodified to the desired page address by performing a load ROM pageregister instruction. Execution of a successful BRANCH will not copy thenew page address into the address register 46, and set the hardware toperform short branches within the new page.

The data transfer from the buffer register 47 to the address register 46operates in the same manner when executing a successful CALLinstruction. Long CALLS can be executed by performing a load ROM pageregister instruction prior to the execution of a CALL instruction.Omitting the Load P-register instruction would result in a short call.

After executing either a long or short call, the contents of the addressregister 46 which contained the preCALL page address is copied into thebuffer register 47. Data transfer between the buffer register 47 andaddress register 46 is inhibited. Thus, the buffer register is used tostore the desired page address upon returning from a subroutine. Becauseof the above feature, it is not possible to perform long branches whilethe machine is in the CALL mode. Likewise, a subroutine cannot containmore than 64 instructions (one full page). It is permitted, however, tomodify the contents of the buffer register 47 when in the CALL mode byexecuting a load ROM page register instruction. This would permit themodification of the return page address when exiting a subroutine.Execution of a RETURN instruction copies the buffer register 47 contentsinto the address register 46, sets the hardware to perform shortbranches and returns the machine to the normal state.

An unsuccessful CALL or BRANCH will have no effect on either the machinestate or the contents of the registers 46 and 47. Any data present ineither of the two page address registers will remain unchanged. That is,if a short CALL or BRANCH was to be performed, the hardware will be setto perform short operations; if a long CALL or BRANCH was initiated, thehardware will be set to perform the long operation. In addition,executing a RETURN in the normal mode is a no-op.

Supplementing the instruction control of the ROM addressing logic, anexternal input in addition to a powerup circuit are included for circuitinitialization. Circuit initialization will set the machine state tonormal, set the page addresses to perform short branches, set the pageaddress contents to the complement of data applied on the four K lines,and serially copy the data present on the K1 line into the programcounter 36.

With no external inputs applied, the program counter 36 will be set tohex word 00 (0) and the page address register 46 set to hex address F(15).

In regard to the instruction set, it will be noted that the adder 50 iscapable of performing two separate, simultaneous functions and providingthree outputs. The two, 4-bit inputs 57 and 58 can be added and comparedto each other providing a true binary sum output, a carry out of the MSDand a comparison indicating if the two binary numbers are equal inmagnitude, that is, identical bit for bit. Compare and carry informationcan be used for setting up call or branching conditions. The sumprovided can be stored in either or both the accumulator and RAM Yregister or it may not be used at all.

Instruction Word Execution Timing

The timing sequence of execution of instruction words may be understoodby reference to FIGS. 24 and 25. In FIG. 24, a series of instructioncycles A, B, C., etc., are shown, with the system clocks 01, 02, 03, 04,05. Consider that in cycle C, the contents of a digit in the memory orRAM 25 are to be transferred to the adder 50 and output to theaccumulator 52. A schematic representation of the operation is seen inFIG. 25. The adder 50 input is valid during 01 of instruction cycle C,shown as 01C. The bit from the RAM 25 comes valid at 0401C at device106, the output line 32 having been precharged on 02B by device 107. Thecommand MTN on line 61-5 becomes valid after 02B when devices 149 comeon in the control PLA 60. The lines 146 of the control PLA are validafter 01C starts. The instruction word on lines 33 is valid during 02Bcoming out of the RO, at output circuit 253. The output decode for theROM at devices 245 and 246 also is effective at 02B, from devices 251,248 and line 35-1. In the ROM, the lines 240 are precharged at 01B, andcontain valid data at 02B. The Y lines 241 are valid at 02B, the device282 having been set up at 01B. The line 281 in the Y decode 27 wasprecharged at 04(01)B and became valid at the last part of 01B. The RO MY address from the program counter was gated in by device 271 at 01B.Assuming that the MTN operation was a result of a branch, then theBRNCAL command on line 163 became valid after the end of 02A, in gate48-7. The RO branch command from lines 33 was gated in here on 02A, andstatus was valid on line 79 during the last half of 02A, after theprecharge of gate 66-1 on 03A ended. Meanwhile, the branch address comesinto the program counter from lines 33 which contained the branchaddress valid at 02A from output 253 of the ROM.

Thus, for an instruction as defined to be executed in cycle C, the datastarts out at point 381 in FIG. 24, the RAM Y address for the data isvalid at point 382, and the ROM instruction starts out on lines 33 atpoint 383. The ROM Y address for this word goes into the decoder 27 atpoint 384. This address became valid at point 385. Status became validfor a branch to this address at point 386, and the branch address wasalso valid at the ROM output at this point 386.

The MOS/LSI Chip

The entire system described above is fabricated in a single MOS/LSI chipas seen greatly enlarged in FIG. 26, wherein all of the major parts arelabelled with the same reference numerals as used in the block diagramof FIG. 3. A P-channel metal gate process is used, with ion implant fordepletion loads. The chip contains more than 28 bonding pads, because itis possible to use it in a package of more than 28 pins if more digitsof display are to be used. Note tht the ROM, RAM, and control PLA occupythe major part of the area of the chip. The chip is about 200 mils on aside.

The Chip Test Functions

The facility for operating the chip in a test mode has been referred to.This mode would ordinarily be used in manufacture, either before orafter the chips are sealed in the typical 28 pin plastic packages. Thechips are made in batches of perhaps 100 all at one time on a siliconslice of 3 inch diameter; many slices would be processed at the sametime. After all of the processing steps are complete, the slice isscribed and broken into individual chips as seen in FIG. 26. The yieldof good devices from this process is sometimes considerably less than100 percent. Tests must be made to find out which slices are good, whichchips on a slice are good, then which final packaged devices are good,since there can be attrition at each process step. This testing couldbecome very time consuming and expensive, because to be absolutelycertain that every one of the 8800 transistors plus the associatedconnections are all perfect, all of the routines of the calculator wouldhave to be implemented. For this reason, the testing mode has beenincluded. The procedure would be to check each of the 1024 instructionwords in the ROM, then exercise several instructions which aresufficient to check the remainder of the circuitry.

The operations available in the test mode are as follows:

First, a ROM word address may be serially loaded into the programcounter 36 via the K1 pin 75-1, which goes into the gate 355 in FIG. 19and thence into the program counter of FIG. 9 via line 350. This isunder control of KC on input 206; when KC is at Vss, KC on line 199disables the feedback circuitry through gate 351 and enables the K1input to the program counter. Thus, in eight machine cycles, or 8 × 2 or16 microseconds, a word address is presented. Each bit is loaded on 01time, as this is when the program counter can accept new data to node168.

Second, a ROM page address may be parallel loaded into the ROM pageaddress register 46 via K1 to K8 lines 75, devices 196, lines 192 andgates 46' of FIG. 10. This path is also enabled by KC being at -Vdd, andthe bits are loaded on 02. Since the word address comes in serially on01, and the page address in parallel on 02, these may be timemultiplexed, so no additional time is needed to load both. Recognizingthat an entire new 8-bit word address is not needed to generate a newROM address, but instead it may be advanced by one bit, it is seen thatall 1024 locations could be addressed in much less than 1024 × 16 or16000 microseconds.

Third, the 8-bit instruction word from the ROM, at the defined address,can be transferred into the program counter 36 from the lines 33 byexternal control. This is implemented by enabling the devices 162, toload R0 to R7 into nodes 164 of stages 36-0 to 36-7 as seen in FIG. 9.The devices 162 are controlled by BRNCAL on line 163, which can begenerated by KC and K2 in gate 48-7 as seen in FIG. 11. This occurs inone machine cycle.

Fourth, the program counter 36 can be shifted out serially via line 165of FIGS. 9 and 18, line 347, and segment output buffer 65-8, again undercontrol of KC on line 199. This may occur one step ahead of, but at thesame time, as a new ROM word address is being loaded in via K1 and line350 of FIG. 19.

In order to test some or all of the ROM locations, the steps one, two,three and four just described would be implemented in order. All of thebits in all 1024 locations could be verified by a suitably designed testmachine in less than about 20 milliseconds, which is much less thanneeded for some complex calculations in normal operation. Thus, vastsavings in test time are possible.

Another test procedure is to load in a word and page address accordingto the first and second steps described above, then allow the machine toexecute the sequence of instructions beginning at that location, thenobserve the results at the output terminals 17 and 18; and/or read outthe last ROM output or address from the program counter after a certainnumber of cycles. This permits testing selected increments, which aresufficient to verify the integrity of the unit. In a typical complexoperation, there are housekeeping routines which would be used again andagain, perhaps hundreds of times, e.g. normallizing. These need not bechecked but once. This procedure allows repetitive routines to beskipped.

It is understood, of course, that writing in and reading out ROMaddresses and contents can be supplemented with reading in simulatedkeyboard entries.

Although the invention has been described with reference to a specificembodiment, this description is not meant to be construed in a limitingsense. Various modifications of the disclosed embodiment, as well asother embodiments of the invention, will become apparent to personsskilled in the art upon reference to the description of the invention.It is therefore contemplated that the appended claims will cover anysuch modifications or embodiments as fall within the true scope of theinvention.

TABLE OF INSTRUCTIONS CALL: 11XXXXXX

Conditional on status; if status line 79 is a logic 0, then the CALLinstruction is not performed. If status is 1, the machine goes into theCALL mode, as indicated by setting the CALL latch 200 to a logic 1. Theprogram counter 36 is stored in the subroutine register 43. The pageaddress is stored in the buffer 47. The contents of the buffer register47 are used as the page address. The W field R2 to R7 of the instructionword is loaded into the program counter 36 via devices 162. Allinstructions executed while in the CALL mode perform their normalfunctions, except for the CALL and branch instructions; execution of aCALL within a CALL mode is not valid; branches executed within a callmode must be intrapage.

Branch (BRNC): 10XXXXXX

Conditional on status; if status is a logic 0, then the branchinstruction is not performed. If status is 1, then the W field is loadedinto the program counter 36 and the contents of the buffer register 47become the new page address in the register 46, except when in the CALLmode. Branch (as well as CALL) can be unconditional because of thenature of status logic 66. Status is normally in logic 1 which is theproper condition for successfully performing a branch or CALL. If theinstruction immediately preceeding the branch or CALL does not affectstatus, then the operation will be successful. Status is valid for onlyone instruction cycle. It is therefore invalid to perform multiple testsbefore a branch operation. Only that instruction immediately preceedingthe branch instruction determines whether branching is successful.Status always returns to logic 1 after a branch instruction.

Load Y Register with a Constant (TRCY): 0100XXXX

The C field of the instruction word, bits R4 thru R7, is transferredinto the Y register 40. This is unconditional, and neither carry norcompare go to status logic 66.

Compare Y Register to a Constant (YNEC): 0101XXXX

The contents of the Y register 40 are compared to the C field of theinstruction word. Compare information on line 67 is input to the statuslogic 66. Inequality will force status to a logical 1. This instructionis not conditional on status.

Constant Store, Increment Y Register (CMIY): 0110XXXX

The contents of the C field is stored directly into the memory locationaddressed by the X and Y registers 73 and 40. The Y register 40 is thenincremented by one. The instruction is not conditional on status, andcarry and compare do not go to status.

Accumulator Less than or Equal to Constant (ALEC): 0111XXXX

The accumulator 52 is subtracted from the C field of the instructionword, using 2's complement addition. Resulting carry information on line67 is input to the status logic 66. If the accumulator is less than orequal to the constant, status will be set to a logic 1. The instructionis unconditional.

Load P Register (LDP): 0001XXXX

The buffer register 47 is loaded with the contents of the C field in theinstruction word. This is unconditional and neither carry nor compare goto status.

Bit Set (SBIT): 001100XX

The contents of the memory location addressed by the X and Y registers73 and 40 is selected. One of the four bits, as selected by the B fieldof the instruction word, is set to a logic 1.

Bit Reset (RBIT): 001101XX

The contents of the RAM 25 memory location addressed by the X and Yregisters 73 and 40 is selected. One of the four bits, as selected bythe B field of the instruction word via CKB logic 56, is reset to alogic 0.

Bit Test (TBIT): 001110XX

The contents of the memory location addressed by the X and Y registers73 and 40 is selected. One of the four bits, as selected by the B fieldof the instruction word via CKB 56, is tested in the adder 50. A logical1 in the selected bit will set status to a logical 1, via compare outputto status on line 67.

Load X Register (LDX): 001111XX

The X or RAM page address register 73 is loaded from the B field of theinstruction word. This is unconditional, and neither carry nor comparego to status logic 66.

Store and Increment (STIN): 00100000

The contents of the accumulator 52 are stored in the RAM memory locationaddressed by the X and Y registers 73 and 40. After completion of thestore operation, the Y register 40 is incremented by one. Unconditional;status is not affected.

Transfer Memory to Accumulator (TRMA): 00100001

The contents of the RAM memory location addressed by the X and Yregisters 73 and 40 is unconditionally transferred into the accumulator52. Memory data in the RAM is unaltered. Unconditional, and carry andcompare do not go to status.

Transfer Memory to Y Register (TRMY): 00100010

The contents of the RAM memory location addressed by the X and Yregisters 73 and 40 is unconditionally transferred into the Y register40. Memory data in the RAM is unaltered.

Transfer Y Register to Accumulator (TYRA): 00100011

The Y register 40 is unconditionally transferred into the accumulator52. Contents of the Y register 40 are unaltered.

Transfer Accumulator to Y Register (TRAY): 00100100

The accumulator 52 is unconditionally transferred into the Y register40. Accumulator contents are unaltered.

Memory and Accumulator Add (AMAA): 00100101

The contents of the accumulator 52 are added to the contents of the RAMmemory location addressed by the X and Y registers 73 and 40 with theresulting sum stored into the accumulator 52. Resulting carryinformation on line 67 is input to the status logic 66. A sum that isgreater than fifteen will set status to a logic 1. The contents of thememory location in the RAM 25 are unaltered.

Compare Memory to Zero (MNEO): 00100110

The RAM memory contents addressed by the X and Y registers 73 and 40 arecompared to zero. Comparison information on line 67 is input to thestatus logic. Inequality between memory and zero will set status 66 to alogic 1.

Memory and Accumulator Subtract (SMAA): 00100111

The contents of the accumulator 52 are subtracted from the contents ofthe RAM memory location addressed by the X and Y registers 73 and 40using 2's complement addition with the difference stored into theaccumulator 52. Resulting carry information is input to status 66.Status will be set to logic 1 if the accumulator is less than or equalto the memory.

Load Incremented Memory (INMA): 00101000

The contents of the RAM memory location addressed by the X and Yregisters 73 and 40 is incremented by one and stored into theaccumulator 52. The original contents of the RAM memory are unaltered.Resulting carry information is input via line 67 to the status logic 66.Status will be set to a logic 1 if the sum is greater than 15.

Accumulator Less than or Equal to Memory (ALEM): 00101001

The accumulator 52 is subtracted from the contents of the RAM memorylocation addressed by the X and Y registers 73 and 40 using 2'scomplement addition. Resulting carry information is input via line 67 tothe status logic 66. Status equal to a logic 1 indicates that theaccumulator is less than or equal to the memory. Memory and accumulatorcontents are unaltered.

Load Decremented Memory (DCMA): 00101010

The contents of the RAM memory location addressed by the X and Yregisters 73 and 40 are decremented by one and loaded into theaccumulator 52. Memory contents are unaltered. Resulting carryinformation is input to the status logic. If memory is greater than orequal to one, status will be set to log 1.

Increment Y register (INY)

The contents of the Y register 40 are incremented by one. Resultingcarry information is input to the status logic 66. A sum greater thanfifteen will set status to a logic 1.

Decrement Y Register (DCY): 00101100

The contents of the Y register 40 are decremented by one. Resultingcarry information is input to the status logic 66. If Y is greater thanor equal to 1, status will be set to a logic 1.

2's Complement of the Accumulator (CIA): 00101101

The contents of the accumulator 52 are subtracted from zero using 2'scomplement addition. The result is stored in the accumulator 52.Resulting carry information is input to the status logic 66. Thisoperation is equivalent to complementing and incrementing theaccumulator. If the accumulator contents are equal to zero, then statuswill be set to a logic 1.

Exchange Memory and Accumulator (EXMA): 00101110

The contents of the RAM memory location addressed by the X and Yregisters 73 and 40 are exchanged with the accumulator 52. That is, theaccumulator is stored into memory and memory is transferred into theaccumulator.

Clear Accumulator (CLA): 00101111

The contents of the accumulator 52 are unconditionally set to zero.

Add Eight to the Accumulator (A8AA): 00000001

The constant 8, as determined by bits R7 thru R4 of the instructionword, is added to the accumulator 52. Resulting carry information isinput to the status logic 66. A sum greater than fifteen will set statusto a logic 1.

Compare Y Register to the Accumulator (YNEA): 00000010

The contents of the Y register 40 are compared to the contents of theaccumulators 52. Comparison information is input to the status logic 66.Inequality between the Y register and the accumulator will set status toa logic 1. The logic state of status 66-1 is also copied into the statuslatch 66-2.

Store Accumulator (STA): 00000011

The contents of the accumulator 52 are stored into the RAM memorylocation addressed by the X and Y registers 73 and 40. Accumulator 52contents are unaffected.

Store and Clear Accumulator (STCLA): 00000100

The contents of the accumulator 52 are stored into the RAM memorylocation addressed by the X and Y registers 73 and 40. The accumulator52 is then reset to zero.

Add 10 to the Accumulator (A10AA): 00000101

The constant (10), as determined by bits R7 and R4 of the instructionword, is added to the accumulator 52.

Add Six to the Accumulator (A6AA): 00000110

The constant six, as determined by bits R7 and R4 of the instructionword, is added to the contents of the accumulator 52. Resulting carryinformation is input to the status logic 66. A result greater thanfifteen will set status to a logic 1.

Decrement Accumulator (DCA): 00000111

The contents of the accumulator 52 are decremented by one. Resultingcarry information is input to the status logic 66. If accumulator isgreater than or equal to one, status will be set to a logic 1.

Increment Accumulator (INA): 00001110

The contents of the accumulator 52 are incremented by one.

Complement X Register (COMX): 00000000

The contents of the X or RAM page address register 73 are logicallycomplemented.

Load External Inputs (TRKA): 00001000

Data present on the four external K input lines 75 is transferred intothe accumulator 52.

Test External Inputs (KNEO): 00001001

Data on the external K input lines 75 is compared to zero. Comparisoninformation is input to the status logic 66. Non-zero external data willset status to a logic 1.

Load Output Register (LDO): 00001010

The contents of the accumulator 52 and the status latch 66-2 aretransferred to the output register 62. The register 62 can be decoded in62 to supply data to as many as eight output lines 17 and is a primaryregister used in data output external to the chip. The contents of the Yregister 40 are also decremented by one.

Clear O Output Register (CLRO): 00001011

The contents of the output register 62 are set to a zero.

Reset D [Y] Output (RSTR): 00001100

If the contents of the Y register 40 are between 0 thru 12 inclusive,then one of the D outputs will be reset to a logic 0. Selection of the Doutput is determined by the decoded contents of the Y register 40. Forvalues greater than 12 in the Y register, the instruction is a no-op tothe user.

Set D [Y] Output (SETR): 00001101

If the contents of the Y register 40 are between 0 thru 12 inclusive,then one of the D outputs will be set to a logic 1. Selection of the Doutput is determined by the decoded contents of the Y register 40. Forvalues greater than 12 in the Y register, the instruction is a no-op tothe user.

Return (RETN): 00001111

When executed in the CALL mode, the contents of the subroutine register43 are transferred into the program counter 36. Simultaneously, thecontents of the buffer register 47 are transferred into the ROM pageaddresss register 46. This operation will return the system to theproper point after a subroutine has been executed.

When a return instruction is executed in the non-CALL mode, that is,when not executing a subroutine, it is a no-operation.

    ______________________________________                                        INSTRUCTION CODE      MNEMONIC                                                ______________________________________                                        1       1       W               CALL                                          1       0       W               BRNC                                          0       100     C               TRCY                                          0       101     C               YNEC                                          0       110     C               CMIY                                          0       111     C               ALEC                                          0       011     00     B        SBIT                                          0       011     01     B        RBIT                                          0       011     10     B        TBIT                                          0       011     11     B        LDX                                           0       010     0000          STIN                                            0       010     0001          TRMA                                            0       010     0010          TRMY                                            0       010     0011          TRYA                                            0       010     0100          TRAY                                            0       010     0101          AMAA                                            0       010     0110          MNEO                                            0       010     0111          SMAA                                            0       010     1000          INMA                                            0       010     1001          ALEM                                            0       010     1010          DCMA                                            0       010     1011          INY                                             0       010     1100          DCY                                             0       010     1101          CIA                                             0       010     1110          EXMA                                            0       010     1111          CLA                                             0       001     C             LDP                                             0       000     0000          COMX                                            0       000     0001          A8AA                                            0       000     0010          YNEA                                            0       000     0011          STA                                             0       000     0100          STCLA                                           0       000     0101          A10AA                                           0       000     0110          A6AA                                            0       000     0111          DCA                                             0       000     1000          TRKA                                            0       000     1001          KNEC                                            0       000     1010          LDO                                             0       000     1011          CLRO                                            0       000     1100          RSTR                                            0       000     1101          SETR                                            0       000     1110          INA                                             0       000     1111          RETN                                            ______________________________________                                    

What is claimed is:
 1. An electronic digital system comprising: datastorage means including a random access memory; addressing means foraddressing the random access memory and accessing therein digitscontaining a plurality of bits in parallel; program storage meansincluding a read-only-memory containing a large number of multi-bitinstruction words for defining the operation of the system; arithmeticmeans for performing arithmetic and logic operations on digits in bitparallel format; control means receiving the instruction words from theread-only-memory in bit parallel, one word at a time, the control meansgenerating commands for defining the operation of the system in responseto the instruction words; input means including a plurality of parallelterminals for data input to the system; multiple function circuityincluded in the system, the multiple function circuitry having inputsfor receiving parts of instruction words and data input from saidparallel terminals and having parallel outputs coupled to the datastorage means and to the arithmetic means for selectively, in responseto said commands, transferring in bit parallel format said parts ofinstruction words and data input in the alternative to the data storagemeans or to the arithmetic means.
 2. A system according to claim 1wherein the multiple function circuitry includes control inputs toreceive commands from the control means to select among the alternativefunctions.
 3. A system according to claim 2 wherein the multiplefunction circuitry includes means for selecting one of its paralleloutputs in response to part of the instruction word.
 4. A systemaccording to claim 3 wherein the means for selecting is actuated inresponse to another part of the instruction word.
 5. A system accordingto claim 4 wherein means are provided for actuating the means forselecting simultaneously with the control means for setting andresetting a bit in the data storage means corresponding to the selectedone of the parallel outputs.
 6. A system according to claim 5 whereinthe system includes means for excluding operation of the means forselecting if the multiple function circuitry is transferring said partsof the instruction words and and data input.
 7. A system according toclaim 1 wherein: the addressing means accesses the random access memoryone digit at a time, and each digit comprises four parallel bits; theinput means comprises four parallel terminals; the instruction word islonger than four bits; said part of the instruction word is 4 bits; thearithmetic means comprises four parallel adder stages.
 8. Digital dataprocessing apparatus comprising: data storage menas having multiple bitparallel inputs; program storage means containing multiple bitinstruction words; arithmetic means having bit parallel inputs; datainput means including a plurality of parallel terminals; combined datatransfer and control circuitry having inputs connected to the programstorage means to receive instruction words and also connected to thedata input means and having outputs connected to the parallel inputs ofthe data storage means and to the bit parallel inputs of the arithmeticmeans; said combined circuitry operating in response to parts of theinstruction words for selectively transferring parts of the instructionwords to the inputs of the data storage means and to the inputs of thearithmetic means, and for selectively transferring information from thedata input means to the inputs of the arithmetic means, and forselectively generating control bits in response to parts of theinstruction words for applying to the inputs of the data storage means.9. Apparatus according to claim 8 wherein the system includes meansresponsive to the instruction words for setting and resetting bits inthe data storage means, such bits in the data storage means beingselected by the control bits.
 10. Apparatus according to claim 8 whereinsaid combined data transfer and control circuitry selectively transfersinformation from the data input means to the inputs of the data storagemeans.
 11. Digital processing apparatus comprising: data storage meanshaving multiple bit parallel inputs; instruction word access means forapplying multiple bit instruction words on a plurality of parallellines; arithmetic means having a plurality of bit-parallel inputs; inputmeans including a plurality of parallel terminals; transfer circuitryhaving inputs connected to parallel lines of the instruction word accessmeans to receive at least parts of the multiple bit instruction wordsand also connected to parallel terminals of the input means, thetransfer circuitry having outputs connected to parallel inputs of thedata storage means and connected to bit-parallel inputs of thearithmetic means; said transfer circuitry including control circuitryresponsive to parts of instruction words on the parallel lines, thetransfer circuitry operating via said control circuitry to selectivelyand in the alternative transfer parts of the instruction words to theparallel inputs of the data storage means or to the bit-parallel inputsof the arithmetic means, and to selectively and in the alternativetransfer information from the parallel terminals of the input means tothe parallel inputs of the data storage means or to the bit-parallelinputs of the arithmetic means.
 12. Digital processing apparatusaccording to claim 11 wherein the apparatus includes control meansresponsive to the instruction words on the plurality of parallel linesfor producing commands for defining the operation of the apparatus, andthe transfer circuitry receives commands from the control means forselecting the operation thereof.